// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  sdmam_ch_regs_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1
// Date          :  2013/3/10
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/04/10 11:32:32 Create file
// ******************************************************************************

#ifndef __SDMAM_CH_REGS_REG_OFFSET_FIELD_H__
#define __SDMAM_CH_REGS_REG_OFFSET_FIELD_H__

#define SDMAM_CH_REGS_CH_QUIESCENT_LEN       1
#define SDMAM_CH_REGS_CH_QUIESCENT_OFFSET    31
#define SDMAM_CH_REGS_CH_FSM_STATUS_LEN      4
#define SDMAM_CH_REGS_CH_FSM_STATUS_OFFSET   16
#define SDMAM_CH_REGS_CH_RETRY_LEN           1
#define SDMAM_CH_REGS_CH_RETRY_OFFSET        6
#define SDMAM_CH_REGS_CH_ABORT_EN_LEN        1
#define SDMAM_CH_REGS_CH_ABORT_EN_OFFSET     5
#define SDMAM_CH_REGS_CH_NS_LEN              1
#define SDMAM_CH_REGS_CH_NS_OFFSET           4
#define SDMAM_CH_REGS_CH_RESET_LEN           1
#define SDMAM_CH_REGS_CH_RESET_OFFSET        3
#define SDMAM_CH_REGS_CH_PAUSE_RESUME_LEN    1
#define SDMAM_CH_REGS_CH_PAUSE_RESUME_OFFSET 2
#define SDMAM_CH_REGS_CH_PAUSE_LEN           1
#define SDMAM_CH_REGS_CH_PAUSE_OFFSET        1
#define SDMAM_CH_REGS_CH_ENABLE_LEN          1
#define SDMAM_CH_REGS_CH_ENABLE_OFFSET       0

#define SDMAM_CH_REGS_PRODUCTID_LEN             8
#define SDMAM_CH_REGS_PRODUCTID_OFFSET          24
#define SDMAM_CH_REGS_VARIANT_LEN               4
#define SDMAM_CH_REGS_VARIANT_OFFSET            16
#define SDMAM_CH_REGS_REVISION_LEN              4
#define SDMAM_CH_REGS_REVISION_OFFSET           12
#define SDMAM_CH_REGS_JEDEC_CONTINUATION_LEN    4
#define SDMAM_CH_REGS_JEDEC_CONTINUATION_OFFSET 8
#define SDMAM_CH_REGS_JEDEC_ID_LEN              7
#define SDMAM_CH_REGS_JEDEC_ID_OFFSET           0

#define SDMAM_CH_REGS_TYPER_QRS_LEN            1
#define SDMAM_CH_REGS_TYPER_QRS_OFFSET         4
#define SDMAM_CH_REGS_TYPER_SRS_LEN            1
#define SDMAM_CH_REGS_TYPER_SRS_OFFSET         3
#define SDMAM_CH_REGS_TYPER_RAS_LEN            1
#define SDMAM_CH_REGS_TYPER_RAS_OFFSET         2
#define SDMAM_CH_REGS_TYPER_DISTRIBUTED_LEN    1
#define SDMAM_CH_REGS_TYPER_DISTRIBUTED_OFFSET 1
#define SDMAM_CH_REGS_TYPER_SQ_ABORT_LEN       1
#define SDMAM_CH_REGS_TYPER_SQ_ABORT_OFFSET    0

#define SDMAM_CH_REGS_CH_ERR_STATUS_LEN    8
#define SDMAM_CH_REGS_CH_ERR_STATUS_OFFSET 20
#define SDMAM_CH_REGS_CH_IOE_STATUS_LEN    1
#define SDMAM_CH_REGS_CH_IOE_STATUS_OFFSET 17
#define SDMAM_CH_REGS_CH_IOC_STATUS_LEN    1
#define SDMAM_CH_REGS_CH_IOC_STATUS_OFFSET 16
#define SDMAM_CH_REGS_CH_IOE_MASK_LEN      1
#define SDMAM_CH_REGS_CH_IOE_MASK_OFFSET   1
#define SDMAM_CH_REGS_CH_IOC_MASK_LEN      1
#define SDMAM_CH_REGS_CH_IOC_MASK_OFFSET   0

#define SDMAM_CH_REGS_SQ_BA_L_LEN    20
#define SDMAM_CH_REGS_SQ_BA_L_OFFSET 12

#define SDMAM_CH_REGS_SQ_BA_H_LEN    16
#define SDMAM_CH_REGS_SQ_BA_H_OFFSET 0

#define SDMAM_CH_REGS_SQ_SHAREABILITY_LEN    2
#define SDMAM_CH_REGS_SQ_SHAREABILITY_OFFSET 20
#define SDMAM_CH_REGS_SQ_CACHEABILITY_LEN    3
#define SDMAM_CH_REGS_SQ_CACHEABILITY_OFFSET 16
#define SDMAM_CH_REGS_SQ_SIZE_LEN            16
#define SDMAM_CH_REGS_SQ_SIZE_OFFSET         0

#define SDMAM_CH_REGS_SQ_TDB_LEN    16
#define SDMAM_CH_REGS_SQ_TDB_OFFSET 0

#define SDMAM_CH_REGS_SQ_HDB_LEN    16
#define SDMAM_CH_REGS_SQ_HDB_OFFSET 0

#define SDMAM_CH_REGS_CQ_BA_L_LEN    20
#define SDMAM_CH_REGS_CQ_BA_L_OFFSET 12

#define SDMAM_CH_REGS_CQ_BA_H_LEN    16
#define SDMAM_CH_REGS_CQ_BA_H_OFFSET 0

#define SDMAM_CH_REGS_CQ_SHAREABILITY_LEN    2
#define SDMAM_CH_REGS_CQ_SHAREABILITY_OFFSET 20
#define SDMAM_CH_REGS_CQ_CACHEABILITY_LEN    3
#define SDMAM_CH_REGS_CQ_CACHEABILITY_OFFSET 16
#define SDMAM_CH_REGS_CQ_SIZE_LEN            16
#define SDMAM_CH_REGS_CQ_SIZE_OFFSET         0

#define SDMAM_CH_REGS_CQ_TDB_LEN    16
#define SDMAM_CH_REGS_CQ_TDB_OFFSET 0

#define SDMAM_CH_REGS_CQ_HDB_LEN    16
#define SDMAM_CH_REGS_CQ_HDB_OFFSET 0

#define SDMAM_CH_REGS_DFX_CTRL0_LEN    32
#define SDMAM_CH_REGS_DFX_CTRL0_OFFSET 0

#define SDMAM_CH_REGS_DFX_INF0_H_LEN    8
#define SDMAM_CH_REGS_DFX_INF0_H_OFFSET 24
#define SDMAM_CH_REGS_DFX_INF0_L_LEN    24
#define SDMAM_CH_REGS_DFX_INF0_L_OFFSET 0

#define SDMAM_CH_REGS_DFX_INF1_LEN    32
#define SDMAM_CH_REGS_DFX_INF1_OFFSET 0

#define SDMAM_CH_REGS_DFX_INF2_LEN    32
#define SDMAM_CH_REGS_DFX_INF2_OFFSET 0

#define SDMAM_CH_REGS_DFX_INF3_LEN    32
#define SDMAM_CH_REGS_DFX_INF3_OFFSET 0

#define SDMAM_CH_REGS_DFX_INF4_LEN    32
#define SDMAM_CH_REGS_DFX_INF4_OFFSET 0

#define SDMAM_CH_REGS_DFX_INF5_LEN    32
#define SDMAM_CH_REGS_DFX_INF5_OFFSET 0

#define SDMAM_CH_REGS_DFX_INF6_LEN    32
#define SDMAM_CH_REGS_DFX_INF6_OFFSET 0

#define SDMAM_CH_REGS_DFX_INF7_LEN    32
#define SDMAM_CH_REGS_DFX_INF7_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT0_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT0_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT1_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT1_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT2_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT2_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT3_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT3_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT4_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT4_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT5_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT5_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT6_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT6_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT7_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT7_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT8_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT8_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT9_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT9_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT10_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT10_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT11_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT11_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT12_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT12_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT13_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT13_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT14_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT14_OFFSET 0

#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT15_LEN    16
#define SDMAM_CH_REGS_DFX_EMU_PRESS_CNT15_OFFSET 0

#endif // __SDMAM_CH_REGS_REG_OFFSET_FIELD_H__
